A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS

This paper presents a 12-bit 100-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for low-power wireless and imaging systems. A split-capacitor digital-to-analog (CDAC) structure is adopted reducing the core area improving sampling speed. The linearity of CDAC calibrated by programming least-significant-bits (LSBs) dummy capacitor. unit capacitor in array customized higher symmetry their mismatch. Our SAR ADC based on logic, its timing controlled delaying block critical path. prototype fabricated 65-nm CMOS process with 1.2 V supply occupies an active 0.029 mm 2 . With rate, measured ENOB scores 10.17 bits 1.5 MHz input figure-of-merit (FoM) 6.94 fJ/conversion-step. It can achieve 8.83 Nyquist signal.